Showing posts with label verilog code. Show all posts
Showing posts with label verilog code. Show all posts
Wednesday, November 11, 2015
32-BIT BARREL SHIFTER IN VERILOG
32-BIT BARREL SHIFTER
module barrel (
input [n:0]in,
input [4:0]sh,
input shift_LeftRight,rotate_LeftRight,
output reg [n:0] out);
parameter n=31;
always@*
begin
if(~shift_LeftRight)
out = in<<sh;
else if(shift_LeftRight)
out = in>>sh;
else
begin
case(sh)
5'b00001:
out=(~rotate_LeftRight)?{in[n-1:0],in[n]}:{in[0],in[n:1]};
5'b00010:
out=(~rotate_LeftRight)?{in[n-2:0],in[n:n-1]}:{in[1:0],in[n:2]};
5'b00011:
out=(~rotate_LeftRight)?{in[n-3:0],in[n:n-2]}:{in[2:0],in[n:3]};
5'b00100:
out=(~rotate_LeftRight)?{in[n-4:0],in[n:n-3]}:{in[3:0],in[n:4]};
5'b00101:
out=(~rotate_LeftRight)?{in[n-5:0],in[n:n-4]}:{in[4:0],in[n:5]};
5'b00110:
out=(~rotate_LeftRight)?{in[n-6:0],in[n:n-5]}:{in[5:0],in[n:6]};
5'b00111:
out=(~rotate_LeftRight)?{in[n-7:0],in[n:n-6]}:{in[6:0],in[n:7]};
5'b01000:
out=(~rotate_LeftRight)?{in[n-8:0],in[n:n-7]}:{in[7:0],in[n:8]};
5'b01001:
out=(~rotate_LeftRight)?{in[n-9:0],in[n:n-8]}:{in[8:0],in[n:9]};
5'b01010:
out=(~rotate_LeftRight)?{in[n-10:0],in[n:n-9]}:{in[9:0],in[n:10]};
5'b01011:
out=(~rotate_LeftRight)?{in[n-11:0],in[n:n-10]}:{in[10:0],in[n:11]};
5'b01100:
out=(~rotate_LeftRight)?{in[n-12:0],in[n:n-11]}:{in[11:0],in[n:12]};
5'b01101:
out=(~rotate_LeftRight)?{in[n-13:0],in[n:n-12]}:{in[12:0],in[n:13]};
5'b01110:
out=(~rotate_LeftRight)?{in[n-14:0],in[n:n-13]}:{in[13:0],in[n:14]};
5'b01111:
out=(~rotate_LeftRight)?{in[n-15:0],in[n:n-14]}:{in[14:0],in[n:15]};
5'b10000:
out=(~rotate_LeftRight)?{in[n-16:0],in[n:n-15]}:{in[15:0],in[n:16]};
5'b10001:
out=(~rotate_LeftRight)?{in[n-17:0],in[n:n-16]}:{in[16:0],in[n:17]};
5'b10010:
out=(~rotate_LeftRight)?{in[n-18:0],in[n:n-17]}:{in[17:0],in[n:18]};
5'b10011:
out=(~rotate_LeftRight)?{in[n-19:0],in[n:n-18]}:{in[18:0],in[n:19]};
5'b10100:
out=(~rotate_LeftRight)?{in[n-20:0],in[n:n-19]}:{in[19:0],in[n:20]};
5'b10101:
out=(~rotate_LeftRight)?{in[n-21:0],in[n:n-20]}:{in[20:0],in[n:21]};
5'b10110:
out=(~rotate_LeftRight)?{in[n-22:0],in[n:n-21]}:{in[21:0],in[n:22]};
5'b10111:
out=(~rotate_LeftRight)?{in[n-23:0],in[n:n-22]}:{in[22:0],in[n:23]};
5'b11000:
out=(~rotate_LeftRight)?{in[n-24:0],in[n:n-23]}:{in[23:0],in[n:24]};
5'b11001:
out=(~rotate_LeftRight)?{in[n-25:0],in[n:n-24]}:{in[24:0],in[n:25]};
5'b11010:
out=(~rotate_LeftRight)?{in[n-26:0],in[n:n-25]}:{in[25:0],in[n:26]};
5'b11011:
out=(~rotate_LeftRight)?{in[n-27:0],in[n:n-26]}:{in[26:0],in[n:27]};
5'b11100:
out=(~rotate_LeftRight)?{in[n-28:0],in[n:n-27]}:{in[27:0],in[n:28]};
5'b11101:
out=(~rotate_LeftRight)?{in[n-29:0],in[n:n-28]}:{in[28:0],in[n:29]};
5'b11110:
out=(~rotate_LeftRight)?{in[n-30:0],in[n:n-29]}:{in[29:0],in[n:30]};
5'b11111:
out=(~rotate_LeftRight)?{in[n-31:0],in[n:n-30]}:{in[30:0],in[n:31]};
default:
out=in;
endcase
end
end
endmodule
`timescale 1ns / 1ps
module barrel_tb #(parameter n=31)();
reg [n:0]in;
reg [5:0]sh;
reg shift_LeftRight,rotate_LeftRight;
wire [n:0] out;
barrel bs(.in(in),.sh(sh),.shift_LeftRight(shift_LeftRight),.rotate_LeftRight(rotate_LeftRight),.out(out));
initial
begin
#1 in=32'b11111111111111110000000000000000;sh=5'b00000;rotate_LeftRight=1'b1;shift_LeftRight=1'bx;
#1 sh=5'b00001;
#1 sh=5'b00010;
#1 sh=5'b00011;
#1 sh=5'b00100;
#1 sh=5'b00101;
#1 sh=5'b00110;
#1 sh=5'b00111;
#1 sh=5'b00000;in=32'b11111111111111110000000000000000;rotate_LeftRight=1'b0;
#1 sh=5'b00001;
#1 sh=5'b00010;
#1 sh=5'b00011;
#1 sh=5'b00100;
#1 sh=5'b00101;
#1 sh=5'b00110;
#1 sh=5'b00000;in=32'b11111111111111110000000000000000;rotate_LeftRight=1'bx;shift_LeftRight=1'b0;
#1 sh=5'b00001;
#1 sh=5'b00010;
#1 sh=5'b00011;
#1 sh=5'b00100;
#1 sh=5'b00101;
#1 sh=5'b00110;
#1 sh=5'b00000;in=32'b11111111111111110000000000000000;shift_LeftRight=1'b1;
#1 sh=5'b00001;
#1 sh=5'b00010;
#1 sh=5'b00011;
#1 sh=5'b00100;
#1 sh=5'b00101;
#1 sh=5'b00110;
end
initial
#32 $finish;
initial begin
// Initialize Inputs
in = 0;
sh = 0;
shift_LeftRight = 0;
rotate_LeftRight = 0;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
end
endmodule
verilog code for washing machine
hello guys....
i am providing u a verilog code for washing machine with testbench....
i am providing u a verilog code for washing machine with testbench....
WASHING MACHINE
module wm(clk,rst,coin, lid_r, d_wash, T, soak,rinse, spin, wash,pause,break);
input clk,rst,coin,lid_r,d_wash,T;
output reg soak,rinse,spin,wash,pause,break;
reg[2:0] cst, nst;
// state assignment
parameter IDLE = 3'b000,
SOAK = 3'b001,
WASH=3'b010,
RINSE=3'b011,
WASH2=3'b100,
RINSE2=3'b101,
SPIN=3'b110,
PAUSH=3'b111;
always @(cst or coin or d_wash or lid_r or T)
begin
case (cst)
IDLE:
if(coin==1)
begin
nst=SOAK;
soak=1;
rinse=0;
spin=0;
wash=0;
pause=0;
break=0;
end
else
begin
nst=cst;
soak=0;
rinse=0;
spin=0;
wash=0;
pause=0;
break=0;
end
SOAK:
if(T==1)
begin
nst=WASH;
soak=0;
rinse=0;
spin=0;
wash=1;
pause=0;
break=0;
end
else
begin
nst=cst;
soak=1;
rinse=0;
spin=0;
wash=0;
pause=0;
break=0;
end
WASH:
if(T==1)
begin
nst=RINSE;
soak=0;
rinse=1;
spin=0;
wash=0;
pause=0;
break=0;
end
else
begin
nst=cst;
soak=0;
rinse=0;
spin=0;
wash=1;
pause=0;
break=0;
end
RINSE:
if(T==1 && d_wash==1)
begin
nst=WASH2;
soak=0;
rinse=0;
spin=0;
wash=1;
pause=0;
break=0;
end
else if(T==1 && d_wash==0)
begin
nst=SPIN;
soak=0;
rinse=0;
spin=1;
wash=0;
pause=0;
break=0;
end
else
begin
nst=cst;
soak=0;
rinse=1;
spin=0;
wash=0;
pause=0;
break=0;
end
WASH2:
if(T==1)
begin
nst=RINSE2;
soak=0;
rinse=1;
spin=0;
wash=0;
pause=0;
break=0;
end
else
begin
nst=cst;
soak=0;
rinse=0;
spin=0;
wash=1;
pause=0;
break=0;
end
RINSE2:
if(T==1)
begin
nst=SPIN;
soak=0;
rinse=0;
spin=1;
wash=0;
pause=0;
break=0;
end
else
begin
nst=cst;
soak=0;
rinse=1;
spin=0;
wash=0;
pause=0;
break=0;
end
SPIN:
if(T==0 && lid_r==1)
begin
nst=PAUSH;
soak=0;
rinse=0;
spin=0;
wash=0;
pause=1;
break=0;
end
else if(T==1)
begin
nst=IDLE;
soak=0;
rinse=0;
spin=0;
wash=0;
pause=0;
break=0;
end
else
begin
nst=cst;
soak=0;
rinse=0;
spin=1;
wash=0;
pause=0;
break=0;
end
PAUSH:
if(lid_r==0)
begin
nst=SPIN;
soak=0;
rinse=0;
spin=1;
wash=0;
pause=0;
break=0;
end
else
begin
nst=cst;
soak=0;
rinse=0;
spin=0;
wash=0;
pause=1;
break=0;
end
default:
nst=IDLE;
endcase
end
always @(posedge clk or negedge rst)
begin
if (rst)
cst <= IDLE;
else
cst <= nst;
end
/*
assign soak = (cst == SOAK);
assign rinse = (cst == RINSE) | (cst == RINSE2);
assign brake = (cst == PAUSE);
assign spin = (cst == SPIN);
assign wash = (cst == WASH) | (cst == WASH2);
*/
endmodule
TEST BENCH
module wm_tb;
reg clk,reset,coin,lid_r,d_wash,T;
wire soak,rinse,spin,wash,pause,break;
wm m1(clk,reset,coin,lid_r,d_wash,T,soak,rinse,spin,wash,pause,break);
initial
begin
$monitor($time, ,,"c=%b",clk,,"t=%b",coin,,"l=%b",lid_r,,"d=%b",d_wash,,"T=%b",T,,"s=%b",soak,,"r=%b",rinse,,"S=%b",spin,,"w=%b",wash,,"p=%b",pause,,"b=%b",break);
reset=0 ;clk=0;coin=0;lid_r=0;d_wash=0;T=0;
#10 coin=1;
#10 T=1;coin=0;
#20 d_wash=1;
#30 lid_r=1;d_wash=0;T=0;
#10 lid_r=0;T=0;
#10 T=1;lid_r=0;
#10 T=1;
#10 coin=1;T=0;
//#10 T=1;
//#10 T=1;
//#5 reset=1;
//#5 reset=0;
end
always
#5 clk=~clk;
initial
#100 $finish ;
endmodule
verilog code for mejority detector
MEJORITY DETECTOR
module majority
(input v1,v2,v3,
output reg m);
always@(v1 or v2 or v3)
begin
if((v1&&v2)|(v2&&v3)|(v3&&v1))
m=1;
else
m=0;
end
endmodule
TESTBENCH
module majority_tb;
reg v1,v2,v3;
wire m;
majority m1(v1,v2,v3,m);
initial
begin
v1=0;v2=0;v3=0;
$monitor($time, ,,v1,v2,v3,,"m=%d",m);
#2 v1=0;v2=0;v3=0;
#2 v1=0;v2=0;v3=1;
#2 v1=0;v2=1;v3=1;
#2 v1=1;v2=0;v3=0;
#2 v1=1;v2=0;v3=1;
#2 v1=1;v2=1;v3=0;
#2 v1=1;v2=1;v3=1;
end
endmodule
You can also check more verilog code onhttp://generaldownload1.blogspot.in/2013/11/all-besic-verilog-code.html
verilog code for counter
COUNTER INCREMENT BY 2
module counter2(r,clk,y);
input r,clk;
output [3:0]y;
reg [3:0]y;
always@(posedge clk or posedge r)
begin
if (r)
y <= 4'b0000;
else
y <= y + 2;
end
endmodule
TESTBENCH
module counter3_tb;
reg r,clk;
wire [3:0]y;
counter2 m1(r,clk,y);
initial
begin
clk=0;
r=0;
$monitor($time, ,,"c=%b",clk,,"r=%b",r,,"y=%b",y);
#5 r=1;
#15 r=0;
#50 $finish;
end
always
begin
#5 clk=~clk;
end
endmodule
OUTPUT
· COUNTER INCREMENT BY 3
module counter2(r,clk,y);
input r,clk;
output [3:0]y;
reg [3:0]y;
always@(posedge clk or posedge r)
begin
if (r)
y <= 4'b0000;
else
y <= y + 3;
end
endmodule
TESTBENCH
module counter3_tb;
reg r,clk;
wire [3:0]y;
counter2 m1(r,clk,y);
initial
begin
clk=0;
r=0;
$monitor($time, ,,"c=%b",clk,,"r=%b",r,,"y=%b",y);
#5 r=1;
#15 r=0;
#50 $finish;
end
always
begin
#5 clk=~clk;
end
endmodule
You can also check more verilog code onhttp://generaldownload1.blogspot.in/2013/11/all-besic-verilog-code.html
verilog code for berral shifter
BERRAL SHIFTER
module bshift
(
input [7:0]a,
input [2:0]sh,
input left,right,
output reg [7:0] b);
always@(a,sh)
begin
if(left)
begin
case(sh)
3'b000: b = a;
3'b001: b = a<<1;
3'b010: b = a<<2;
3'b011: b = a<<3;
3'b100: b = a<<4;
3'b101: b = a<<5;
3'b110: b = a<<6;
3'b111: b = a<<7;
endcase
end
if(right)
begin
case(sh)
3'b000: b = a;
3'b001: b = a>>1;
3'b010: b = a>>2;
3'b011: b = a>>3;
3'b100: b = a>>4;
3'b101: b = a>>5;
3'b110: b = a>>6;
3'b111: b = a>>7;
endcase
end
end
endmodule
TESTBENCH
module bshift_tb;
reg [7:0] a;
reg [2:0] sh,left,right;
wire [7:0] b;
bshift bs(a,sh,left,right,b);
initial
begin
sh=3'b000;a=8'b11111111;left=1'b1;right=1'b0;
$monitor($time, ,"lef","ft=",left, ,"rig","ht=",right, ,"shi","ft", ,"%b",sh, ,"inp","ut", ,"%b",a, ,"out","put", ,"%b",b);
end
always
#1 sh=sh+1;
initial
#9 left=1'b0;
initial
#10 right=1'b1;
initial
#18 $stop;
endmodule
You can also check more verilog code onhttp://generaldownload1.blogspot.in/2013/11/all-besic-verilog-code.html
Subscribe to:
Posts (Atom)