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 4-BIT RIPPLE CARRY ADDER USING FULL ADDER

           
module rip2(s,cout,a,b,cin);
  input [3:0]a;
  input [3:0]b;
  input cin;
  output cout;
  output [3:0]s;
  wire c2,c3,c4,cout;
  fa m1(s[0],c2,a[0],b[0],cin);
  fa m2(s[1],c3,a[1],b[1],c2);
  fa m3(s[2],c4,a[2],b[2],c3);
  fa m4(s[3],cout,a[3],b[3],c4);
endmodule

TESTBENCH

module fa(s,cout,a,b,cin);
input a,b,cin;
output s,cout;
wire w1,w2,w3;
ha m1(w1,w2,a,b);
ha m2(s,w3,w1,cin);
or m3(cout,w2,w3);
endmodule

module ha(s,cout,a,b);      //sub module for Half adder
  input a,b;
  output s,cout;
  xor m1(s,a,b);
  and m2(cout,a,b);
endmodule

module rip2_tb;
reg [3:0]a;
reg [3:0]b;
reg cin;
wire cout;
wire [3:0]s;
rip2 m1(s,cout,a,b,cin);
initial
begin
a=4'b0000;b=4'b0000;cin=0;
$monitor($time, ,,"a=%b",a,,"b=%b",b,,"c=%b",cin,,"d=%b",cout,,"s=%b",s);
#5 a=4'b0000;b=4'b0000;cin=0;
#5 a=4'b0001;b=4'b0000;cin=1;
#5 a=4'b1100;b=4'b1100;cin=1;
#5 a=4'b1100;b=4'b1100;cin=0;
#5 a=4'b1101;b=4'b1101;cin=1;
#5 a=4'b0001;b=4'b1000;cin=1;
#5 a=4'b0000;b=4'b1111;cin=1;
#5 a=4'b1100;b=4'b1100;cin=0;
#5 a=4'b0000;b=4'b0111;cin=1;
#5 a=4'b1100;b=4'b0010;cin=1;
end
endmodule

You can also check more verilog code on

http://generaldownload1.blogspot.in/2013/11/all-besic-verilog-code.html