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N-BIT  GRAY TO BINARY CONVERTER

module binary2gray #(parameter n=4)
(
input [n-1:0] g,
output [n-1:0] b
);
assign b={g[n],b[n:1]^g[n-1:0]};
endmodule

TESTBENCH

module binary2gray_tb;
parameter n=4;
reg [n-1:0]g;
wire [n-1:0]b;
binary2gray b2g(.b(b),.g(g));
initial
begin
#1 g=4'b1111;
$monitor($time,  ,"gra","y","%b",g, ,"bin","ary","%b",b);
end

always

#1 g=g+1;

initial
#10 $stop;
endmodule

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http://generaldownload1.blogspot.in/2013/11/all-besic-verilog-code.html